MIPS32 Architecture for Programmers – Volume IV-f: The MIPS MT Application-Specific Extension to the MIPS32 Architecture

Description

TABLE OF CONTENTS

1.1 Background
1.2 Definitions and General Description
2.1 Multithreaded Execution
2.2 MIPS MT Exception Model
2.3 New Exception Conditions
2.4 New Exception Priority
2.5 Interrupts
2.6 Bus Error Exceptions
2.7 Cache Error Exceptions
2.8 EJTAG Debug Exceptions
2.9 Shadow Register Sets
3.1 New Instructions
4.1 Privileged Resource Architecture for MIPS MT
4.2 MVPControl Register (CP0 Register 0, Select 1)
4.3 MVPConf0 Register (CP0 Register 0, Select 2)
4.4 MVPConf1 Register (CP0 Register 0, Select 3)
4.5 VPEControl Register (CP0 Register 1, Select 1)
4.6 VPEConf0 Register(CP0 Register 1, Select 2)
4.7 VPEConf1 Register(CP0 Register 1, Select 3)
4.8 YQMask Register (CP0 Register 1, Select 4)
4.9 VPESchedule Register (CP0 Register 1, Select 5)
4.10 VPEScheFBack Register (CP0 Register 1, Select 6)
4.11 VPEOpt Register(CP0 Register 1, Select 7)
4.12 TCStatus Register (CP0 Register 2, Select 1)
4.13 TCBind Register (CP0 Register 2, Select 2)
4.14 TCRestart Register (CP0 Register 2, Select 3)
4.15 TCHalt Register (CP0 Register 2, Select 4)
4.16 TCContext Register (CP0 Register 2, Select 5)
4.17 TCSchedule Register (CP0 Register 2, Select 6)
4.18 TCScheFBack Register (CP0 Register 2, Select 7)
4.19 SRSConf0 (CP0 Register 6, Select 1)
4.20 SRSConf1 (CP0 Register 6, Select 2)
4.21 SRSConf2 (CP0 Register 6, Select 3)
4.22 SRSConf3 (CP0 Register 6, Select 4)
4.23 SRSConf4 (CP0 Register 6, Select 5)
4.24 Modifications to Existing MIPS Privileged Resource Architecture
4.25 Thread State as a Function of Privileged Resource State
4.26 Thread Allocation and Initialization Without FORK
4.27 Thread Termination and Deallocation without YIELD
4.28 Multithreading and Coprocessors
5.1 WAIT Instructions
5.2 SC Instructions
6.1 Multi-VPE Processors
6.2 Reset and Virtual Processor Configuration
6.3 MIPS MT and Cache Configuration
7.1 Gating Storage
8.1 EJTAG Debug Resources
8.2 Debug Exception Handling
Appendix A Inter-Thread Communication Storage
Appendix B Revision History

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