MIPS32 Architecture For Programmers – Volume III: The MIPS32 Privileged Resource Architecture
Download PDF book “MIPS32 Architecture For Programmers, Volume III : The MIPS32 Privileged Resource Architecture” (EN) 151 pages Doc No: MD00090 Revision 2.50 July 1, 2005 zip
Description
This PDF book is Volume III of “MIPS32 Architecture for Programmers”.
MIPS32 Architecture for Programmers – Volume III : The MIPS32 Privileged Resource Architecture
The MIPS32 Architecture For Programmers Volume III comes as a multi-volume set.
Volume III describes the MIPS32 Privileged Resource Architecture which defines and governs the behavior of the privileged resources included in a MIPS32 processor implementation.
(PDF) BOOK in English (EN) language.
CONTENTS:
Chapter 1. ABOUT THIS BOOK
1.1 Typographical Conventions
1.2 UNPREDICTABLE and UNDEFINED
1.3 Special Symbols in Pseudocode Notation
1.4 For More Information
Chapter 2. THE MIPS32 PRIVILEGED RESOURCE ARCHITECTURE
2.1 Introduction
2.2 The MIPS Coprocessor Model
Chapter 3. MIPS32 OPERATING MODES
3.1 Debug Mode
3.2 Kernel Mode
3.3 Supervisor Mode
3.4 User Mode
3.5 Other Modes
Chapter 4. VIRTUAL MEMORY
4.1 Support in Release 1 and Release 2 of the Architecture
4.2 Terminology
4.3 Virtual Address Spaces
4.4 Compliance
4.5 Access Control as a Function of Address and Operating Mode
4.6 Address Translation and Cache Coherency Attributes for the kseg0 and kseg1 Segments
4.7 Address Translation for the kuseg Segment when StatusERL = 1
4.8 Special Behavior for the kseg3 Segment when DebugDM = 1
4.9 TLB-Based Virtual Address Translation
Chapter 5. INTERRUPTS AND EXCEPTIONS
5.1 Interrupts
5.2 Exceptions
Chapter 6. GPR SHADOW REGISTERS
6.1 Introduction to Shadow Sets
6.2 Support Instructions
Chapter 7. CP0 HAZARDS
7.1 Introduction
7.2 Types of Hazards
7.3 Hazard Clearing Instructions and Events
Chapter 8. COPROCESSOR 0 REGISTERS
Appendix A. Alternative MMU Organizations
Appendix B. Revision History
List of Figures
List of Tables
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